Your Responsibilities:

1. Carry out all MCO development activities in the field of analog design on own initiative
   
2. Perform chip die size estimation in the product definition phase, and generate chip floorplan based on early stage netlist and perform improvement according to netlist updating
   
3. Generate chip layout with Cadence tools, by performing placement and routing, and generate analog IP layout as needed
   
4. Generate clock tree with Cadence tools and perform timing improvement with feedback from timing analysis
   
5. Perform physical verification like DRC and LVS and perform chip releasing and PCM
   
6. Communicate within a design team and within the whole development organization
   
7. Guarantee the technical deliverables of his jobs in terms of quality and performance
   
8. To develop his/her leadership on his/her domain of skills and actions

Your Profile:

1. Qualification:?MSEE or BSEE, English understanding / speaking/ writing
   
2. Working Experience:? Minimum of 3-5 years experience for layout design
   
3. Expertise / Skills :
   a)Familiar with and has the design experience Cadence layout design tools: First Encounter, Virtusuo, PCM, etc
   b)Specific knowledge of the relevant technical areas
   c)Able to establish good relationships with a multi-disciplinary development team, international customers and subcontractors
   d)Creative thinker with helicopter view, capable of finding an appropriate solution to complex problems
   e)Team/Project leadership